1. Field of the Invention
The present invention relates to a VLSI design automation system, and more particularly to an automatic circuit translation method which automatically translates a circuit element representation required when a circuit having the same function is to be realized by a different device.
2. Description of the Prior Art
There has hitherto been known an automatic circuit translation method which is intended for the automatic generation of logic circuits and which automatically generates logic gates from the boolean representation of a circuit function and which makes it automatic to realize a given individual boolean equation logic gates in the smallest possible number.
In contrast, the circuit translation intended by the present invention consists in that the element of a circuit to be translated is automatically translated by utilizing translation rules which vary depending upon the multifarious connective relations of a particular element with the peripheral elements thereof.